git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 6e0c349a8a59959c3d3571b5f6776bc2d2ca62bc Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Wed, 18 Sep 2024 15:32:54 +0200
   4 Subject: [PATCH 3/4] phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in
   5  airoha_pcie_phy_init_ssc_jcpll()
   6
   7 Fix typo configuring REG_CSR_2L_JCPLL_SDM_HREN register in
   8 airoha_pcie_phy_init_ssc_jcpll routine.
   9
  10 Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
  11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 ---
  13  drivers/phy/phy-airoha-pcie.c | 2 +-
  14  1 file changed, 1 insertion(+), 1 deletion(-)
  15
  16 --- a/drivers/phy/phy-airoha-pcie.c
  17 +++ b/drivers/phy/phy-airoha-pcie.c
  18 @@ -802,7 +802,7 @@ static void airoha_pcie_phy_init_ssc_jcp
  19         airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SDM_IFM,
  20                                    CSR_2L_PXP_JCPLL_SDM_IFM);
  21         airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SDM_HREN,
  22 -                                  REG_CSR_2L_JCPLL_SDM_HREN);
  23 +                                  CSR_2L_PXP_JCPLL_SDM_HREN);
  24         airoha_phy_csr_2l_clear_bits(pcie_phy, REG_CSR_2L_JCPLL_RST_DLY,
  25                                      CSR_2L_PXP_JCPLL_SDM_DI_EN);
  26         airoha_phy_csr_2l_set_bits(pcie_phy, REG_CSR_2L_JCPLL_SSC,